1. Field of the Invention
The present invention generally relates to a logic circuit and its design method. The invention particularly relates to a logic circuit with a pipelined structure and its design method, capable of shortening a cycle time of an operation clock of logic LSI's such as microprocessors and DSP's (digital signal processors) and improving a processing speed of the logic circuit.
2. Description of the Related Art
A logic circuit is mainly divided into a combinational circuit in which a change in an input signal propagates toward the output and influences an output signal value and a sequential circuit or a memory circuit with a function of holding a value or changing a held value in response to a control signal such as a clock signal. The combinational circuit includes fundamental logic elements (e.g., AND gates and NOT gates) having a function of arithmetic operation. The memory circuit may be a flip-flop, a latch, or the like.
In order to obtain a high performance of logic LSI's such as microprocessors and DSP's, in addition to parallel processing, the shortening of an operation cycle is carried out. In order to shorten the operation cycle of a logic LSI, it is essential to shorten the operation cycle of a logic circuit which is a main constituent of the logic LSI. The operation cycle of a logic circuit has been conventionally shortened by development of semiconductor device technology and by utilizing the leading edge circuit technology such as dynamic circuits.
In order to meet the market needs, high speed processing is required. To this end, recently, logic circuits are pipelined to shorten the operation cycle.
FIG. 1 shows a general logic circuit having a simple pipelined structure. This logic circuit has a combinational circuit 803 as a pipeline arithmetic circuit (first stage) and flip-flops 804 and 805 respectively connected to the input and output sides of the combinational circuit 803 for holding-signals. At the rising edge of a clock signal CK, the flip-flops 804 and 805 respectively input (sample) an input signal 801 and an output signal 807 from the combinational circuit 803, the held signals being output to the combinational circuit 803 and the next stage combinational circuit (second stage) 813 as signals 806 and 802, respectively. The clock signal CK periodically changes its value at a preset cycle time. A general logic circuit operates synchronously with this clock. FIG. 2 shows a clock signal waveform input to a logic circuit such as shown in FIG. 1. A cycle time of a logic circuit using a flip-flop operating in response to the rising edge of an input clock is illustrated in FIG. 2.
A time required for a change in an input signal to the combinational circuit to reach an output signal is called a signal propagation delay or a signal propagation time. This signal propagation time changes greatly depending on the circuit conditions and the way an input signal changes. A signal path with a longest signal propagation time is called a critical path of the circuit. In order to guarantee a circuit normal operation, the cycle time of a logic circuit is required to be set longer than the signal propagation time of the critical path of the circuit. This signal propagation time of the critical path sometimes contains a signal propagation time of a memory circuit such as a latch, depending upon circuit design.
Conventional design of a logic circuit has tried to shorten the signal propagation time of the critical path of the circuit in order to shorten the cycle time.
However, there is a limit in merely shortening the cycle time of the operation clock by shortening the signal propagation time of the critical path of a logic circuit. New technology for realizing a faster logic circuit has therefore been desired.
As above, if the logic circuit is pipelined, the arithmetic operation cycle can be shortened and the throughput of arithmetic operation is improved. However, a time from an arithmetic operation start to when the arithmetic results can be used, i.e., so-called latency, becomes large. In general processes, there are a number of processes which use the arithmetic results of the preceding stage arithmetic operation. Therefore, even if the logic circuit is pipelined and the operation cycle is shortened, these effects are not satisfactory from the viewpoint of performance.